The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent the work is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
A signal path between a transmitter and a receiver (e.g., a receiver path of a serial data interface) includes a communication channel. A signal transmitted via the communication channel may be modified by noise, interference, and/or frequency-dependent attenuation. Frequency-dependent attenuation can introduce distortions into the transmitted signal. For example, the distortions may include inter-symbol interference (ISI) and jitter. The distortions may cause errors in the signal as received by the receiver.
The communication channel may be implemented using differential signaling. Differential signaling can reduce the effects of some forms of interference, such as common mode noise. Equalizers such as Continuous Time Linear Equalizers (CTLEs) may be used in communication channels to partially compensate for channel attenuation. A CTLE may be implemented as a differential amplifier with a fixed or programmable frequency dependent degeneration feature. For example, programmable frequency dependent degeneration may be implemented, which allows adjusting one or more resistance and/or capacitance values in the differential amplifier. The resistance and capacitance values may also define a “roll up point,” which refers to a minimum frequency at which the differential amplifier will start to boost the output signal of the differential amplifier.
FIG. 1 shows a receiver path 100 (e.g., of a serial data receiver) including a communication channel 104, an equalizer 108, a sampler 112, a summer 116, a decision feedback estimation (DFE) module 120, and a slicer 124. The equalizer 108 may be, for example, a switched continuous time linear equalizer (CTLE) or a switched CTLE with an integrated sampler.
The equalizer 108 receives an input signal 128 via the communication channel 104 and generates an output signal 132. Each of the input signal 128 and the output signal 132 may include a differential signal pair. The equalizer 108 performs equalization on the input signal 128 to generate the output signal 132. For example, the equalizer 108 may include a differential amplifier.
The input signal 128 received from the communication channel 104 may include attenuation (e.g., frequency dependent attenuation). For example, the frequency dependent attenuation caused by skin effect and dielectric loss, which are two possible sources of attenuation in the communication channel 104, is proportional to a square root of a frequency and the frequency, respectively. The equalizer 108 compensates for any attenuation in the input signal 128 to generate the output signal 132.
The sampler 112 samples the output signal 132 to generate a sampled signal 136. The summer 116 receives the sampled signal 136 and an output 140 of the DFE module 120. For example, the summer 116 may add one or more signals to the sampled signal 136 or subtract one or more signals from the sampled signal 136. The slicer 124 receives an output 144 of the summer 116 and determines a digital value corresponding to the input signal 128. The slicer 124 generates a digital output 148 that is, for example, a digital high (e.g., “1”) or a digital low (e.g., “0”). In some implementations, the slicer 124 may determine a multi-bit digital value that corresponds to the input signal 128 and generate a corresponding multi-bit digital output 148. In some implementations, the summer 116 and the DFE module 120 may be omitted and the equalizer 108 is instead connected directly to the slicer 124.
FIG. 2 shows an example equalizer (e.g., a CTLE) 200. The equalizer 200 includes a first active device 204 and a second active device 208. The first active device 204 and the second active device 208 may include, for example, transistors (e.g., NMOS transistors). The first active device 204 and the second active device 208 receive a differential input signal 212 including a pair of differential inputs 216 and 220, respectively. The equalizer 200 generates a differential output signal 224 including a pair of differential outputs 228 and 232.
The equalizer 200 includes a resistor 236 and a capacitor 240 connected in parallel between the first active device 204 and the second active device 208. The resistor 236 may be a variable resistor including an electronically-controlled circuit having a variable resistance. The capacitor 240 may be a variable capacitor including an electronically-controlled circuit having a variable capacitance. Frequency dependent degeneration of the equalizer 200 may be programmed by adjusting the values of the resistor 236 and the capacitor 240. For example, the resistance and capacitance values of the resistor 236 and the capacitor 240, respectively, define a “roll up point,” which refers to a frequency at which the equalizer 200 begins to boost the differential output signal 224 of the equalizer 200.
A power supply voltage 244 is provided to the equalizer 200 and is connected to the first active device 204 and the second active device 208 via a first load resistor 248, a second load resistor 252, a first load capacitor 256, and a second load capacitor 260. The capacitance values of each of the load capacitors 256 and 260 may represent parasitic capacitances in circuitry of a corresponding portion of the equalizer 200 and/or a capacitance of circuitry that is external to the equalizer 200. Similarly, values of each of the load resistors 248 and 252 may represent a resistance corresponding to leakage currents in circuitry of a corresponding portion of the equalizer 200 and/or a resistance of circuitry that is external to the equalizer 200. The resistance values of the load resistors 248 and 252 may be programmable values.
A first tail current Itail1 controlled by a first current source 264 and a second tail current Itail1 controlled by a second current source 268 are connected to ground 272. The first current source 268 and the second current source 272 may be configured such that the first tail current Itail1 has approximately the same magnitude and direction as that of the second tail current Itail1. Accordingly, each of the currents Itail1 and Itail2 correspond to one half of an overall current Itail (i.e., 0.5*Itail) flowing from the power supply voltage 244 to ground 272.